FIG. 1 illustrates a conventional digital delay locked loop (DLL) circuit. The digital DLL circuit includes a delay generation unit 1, and decoders 2a and 2b for selecting a delay time that is generated at the delay generation unit 1. The delay generation unit 1 is provided with multiple delay element arrays 4a to 4d (in FIG. 1, four arrays) to which multiple delay elements 3 are coupled in a column direction (along X direction), and respective delay elements 5a to 5d are arranged adjacent to respective delay element arrays 4a to 4d. Delay times of respective delay elements 3 and those of 5a to 5d are the same.
In the delay generation unit 1, an input clock signal CLKin that is input to the delay element 5a is output to the delay element 5d as an output clock signal CLKout via each of the delay element arrays 4a to 4d and the delay elements 5b and 5c. A delay time of the output clock signal CLKout for the input clock signal CLKin is adjusted at the decoders 2a and 2b by selecting the number of the delay elements in delay element arrays 4a to 4d and the delay elements 5a to 5d where the clock signal passes.
The decoder 2a outputs a selection signal SLy1 obtained by decoding the input code “icode” to delay elements 3 which are located in the row direction (Y direction) of the delay element arrays 4a to 4d. A delay time for an output clock signal CLKout may be adjusted by increasing or decreasing the number of delay elements in units of four that are serially coupled between 5a and 5d by each selection signal SLy1.
The decoder 2b outputs a selection signal SLy2 that is obtained by decoding an input code “icode” to each of the delay elements 5a to 5d. Then, the delay elements 5a to 5d are selected by each selection signal SLy2 in a range of 1 to 4.
Thus, the delay time for the output clock signal CLKout may be adjusted for a delay time of one delay element as a minimum step by the selection signals SLy1 and SLy2.
The above described digital DLL circuit may adjust a delay time by operation of the decoder 2a and the decoder 2b for a delay time of one delay element as a minimum step. However, delay times for selected delay elements in the row direction of delay element arrays 4a to 4d and for delay elements 5a to 5d do not match due to differences in wiring capacity, etc.
As a result, as illustrated in FIG. 2, when the input code “icode” is sequentially changed, especially when delay elements are increased in units of four by the selection signal SLy1, there is a drawback that linearity of the changes in the delay time DT is deteriorated.
Japanese Laid-open Patent Publication No. H 8-37448 discloses a ring oscillator that provides multiple oscillation characteristics by selecting outputs of multiple unit delay units at a selector circuit and feeding the outputs back to unit delay units of a first stage. However, the publication does not disclose a method to improve linearity of the adjusted delay times.
Japanese Laid-open Patent Publication No. H 6-326570 discloses a variable delay circuit that improves linearity of the delay characteristics by selecting delay signals output from a delay gate circuit coupled in cascade at a selector.
However, in order to select delay signals output from each delay gate circuit, the number of selectors required may be as many as the number of delay gate circuits. As a result, the scale of the circuit increases. Moreover, multiple selectors are serially interposed on the output route of delay signals, thus, variations in selectors lead to variations in delay signals. Hence, sufficient linearity may not be achieved if a variable delay circuit is configured in which a delay signal is selected at a very small delay step with many stages.